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Chapter 2: Important ISE Design Suite 13 Release Information
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The Fixed-Point Toolbox is required if a Gateway Out block has an output greater
than 53 bits. Signals internal to the Xilinx Gateway In and Gateway Out blocks can be
larger than 53 bits without needing the Fixed-Point Toolbox.
For Linux, MATLAB 2010a requires the Red Hat Enterprise Desktop 5.2, 32-bit/64-bit
Operating System. It does not work with Red Hat Enterprise Linux WS v4.7.
New Blocks
Complex Multiply 5.0
This block is based on the Xilinx? LogiCORE? IP Complex Multiplier that implements
AXI4-Stream compliant, high performance, optimized complex multipliers based on user-
specified options.
DSP48 Macro 2.1
The Xilinx LogiCORE? DSP48 Macro provides an easy-to-use interface that abstracts the
XtremeDSP? slice and simplifies its dynamic operation by enabling the specification of
multiple operations via a set of user-defined arithmetic expressions. New in this version of
the core is the ability to control resets and clock enables of the registers within the
XtremeDSP Slice.
DSP48E1
The Xilinx DSP48E1 block is an efficient building block for DSP applications that use Xilinx
Virtex?-6 devices. The DSP48E1 block provides access to the pre-added and control of the
registers within the silicon.
FIR Compiler 6.2
This block is based on the Xilinx? LogiCORE? IP FIR Compiler v6.2 that implements
AXI4-Stream compliant, high performance, optimized complex multipliers based on user-
specified options.
VDMA Interface 3.0 (Beta)
This block is based on the AXI Video Direct Memory Access (AXI VDMA) core which is a
soft Xilinx IP core providing high-bandwidth direct memory access between external DDR
memory and the AXI4-Stream interface. Initialization, status, and management registers
are accessed through an AXI4-Lite slave interface which can be configured using an
MCode block. A MATLAB utility function is provided to generate the necessary logic to
easily connect your System Generator design to external DDR memory.
Previous Versions of System Generator for DSP Release Notes
Previous versions of System Generator for DSP release notes are located in Chapter 3 of the
System Generator for DSP Getting Started Guide (v 12.4) . This getting started guide is
located online at the following URL:
http://www.xilinx.com/support/documentation/dt_sysgendsp_sysgen12-4.htm
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www.xilinx.com
ISE Design Suite 13: Release Notes Guide
UG631 (v 13.1)
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相关PDF资料
EF-EDK-FL SOFTWARE EDK EMBED FLOAT
EF-ISE-DSP-FL SOFTWARE ISE DSP EDITION
EF-ISE-SYSTEM-FL ISE DESIGN SYST FLOATING LICENSE
EF-VIVADO-HLS-FL VIVADO HLS, FLOATING LICENSE
EFM32-GXXX-PTB BOARD PROTOTYPING FOR EFM32
EFS315 FUSE INDUST 315A 415V BS IEC
EHBNCSCB CONN EH BNC T/H SOLDER CUP BLK
EHE004 BOARD ENERGY HARVESTING
相关代理商/技术参数
EF-DSP-PC-NL 功能描述:SOFTWARE SYS GEN FOR DSP RoHS:是 类别:编程器，开发系统 >> 软件 系列:ISE® 设计套件 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384
EFDSS645B25A 制造商:Panasonic Industrial Company 功能描述:DELAY LINE
EFDST645B15B 制造商:Panasonic Industrial Company 功能描述:DELAY LINE
EFE01A 制造商:未知厂家 制造商全称:未知厂家 功能描述:THYRISTOR MODULE|BRIDGE|HALF-CNTLD|CC|200V V(RRM)
EFE01A-F 制造商:未知厂家 制造商全称:未知厂家 功能描述:THYRISTOR MODULE|BRIDGE|HALF-CNTLD|CC|200V V(RRM)
EFE01A-S 制造商:未知厂家 制造商全称:未知厂家 功能描述:THYRISTOR MODULE|BRIDGE|HALF-CNTLD|CC|200V V(RRM)
EFE01A-SE 制造商:未知厂家 制造商全称:未知厂家 功能描述:THYRISTOR MODULE|BRIDGE|HALF-CNTLD|CC|200V V(RRM)
EFE01B 制造商:CRYDOM 制造商全称:Crydom Inc., 功能描述:Power Modules